This invention relates to systems for processing data, and more particularly to means for determining the priority among a plurality of sources contending to provide data to a common, shared data bus.
It is a well known and frequently employed technique in data processing to connect a plurality of sources of data to a single channel or bus adapted to receive data from all of the sources. For example, two or more disc drives, tape drives, or the like can be joined in this manner to a single central processing unit through a plurality of input/output processors. In addition, a plurality of CPU's or instruction processors may provide additional sources of data to the common channel and thus contend for its use along with the input/output processors. The instruction processors typically contain programs including commands, instructions and routines stored in the CPU to direct operation of the data handling system. This multiple source contention for a single bus or channel gives rise to the need to distinguish and to determine priority among the competing sources.
One time honored approach is to assign individual, sequential priority. For example, U.S. Pat. No. 3,534,339 (Rosenblatt) discloses a system which encodes identification bits of multiple active devices simultaneously, and selects the identification bits corresponding to a request signal from the highest priority device. Similarly, in U.S. Pat. No. 3,425,037 (Patterson), signals from all peripheral devices sharing a common connection are monitored, with a request signal from each inhibited if the monitoring means senses a higher priority request. Other directly sequential priority systems are disclosed in U.S. Pat. No. 4,745,548 (Blahut) and U.S. Pat. No. 3,353,160 (Lindquist).
Alternatively, priority may be determined by sensing less than all of the sources. For example, U.S. Pat. No. 3,832,692 (Henzel) discloses a plurality of priority seeking devices sharing a common bus. Each device "looks back" in the sense of determining the priority indications of two or more previous (higher priority) devices, and thus gains access to the bus only if the previous two or more devices are not requesting such access.
Yet another technique is to determine priority by enabling data sources to interrupt access of lower priority sources sharing the channel. In U.S. Pat. No. 3,643,229 (Stuebe), a series of stored programs including commands, instructions and routines, can individually interrogate the CPU memory and retrieve addresses of command sequences. An interrupt arrangement allows the CPU to interrupt a program being executed and shift to and execute a higher priority command sequence, returning to the original program after such execution. U.S. Pat. No. 3,473,155 (Couleur) discloses a somewhat similar system for determining priority among peripheral units.
The aforementioned sequential systems, however, tend to over-utilize the sources of highest priority and under-utilize the lowest priority sources. This disadvantage can be limited by limiting the number of separate sources sharing the common channel, or by employing additional circuitry or logic to counter the imbalance. For example, U.S. Pat. No. 3,676,860 (Collier) discloses a system in which competing processors each have a request phase and a control phase, with a priority system determining which among several processors can move from the request to the control phase. A register which determines priorities is modified each time a connection is established by one of the processors. In U.S. Pat. No. 3,399,384 (Crockett), each of a plurality of peripheral devices can issue demand signals of differing priorities. Consequently, final priority is determined by the level of the request, and by a pre-assigned priority among the peripheral devices.
Typically, input/output data must be handled rapidly and virtually as soon as it is presented, while data from instruction processors can be maintained for later use. One known approach is to use a timer to control clearing of a register having high and low priority sectors. The timer sets a predetermined period during which, as long as the high priority sector is being serviced, prevents the low priority sector from being cleared, then permits a shift to the low priority register for a single clearance while the timer is reset. While each of the above systems can be somewhat satisfactorily employed in setting priorities among data sources, none is directed to establishing a general, higher priority for sources of input/output data as opposed to other CPU's, to adequately handle input from other CPU's without requiring a timer.
Therefore, it is an object of the present invention to provide a means for assigning a higher priority to input/output data, for facilitating a more immediate and rapid handling of such data as opposed to data from instruction processors.
Another object is to provide a simple and reliable priority system which, in cooperation with a sequential priority system, designates input/output data for more rapid and immediate handling as opposed to internal processing instructions.
Yet another object of the invention is to provide a bifurcated register means, including a sector for input/output data and a sector for processing instructions, each with multiple latches, and a means for clearing the first sector of the register each time a single latch is cleared from the second sector.